rev. 3.0 october 2010 www.aosmd.com page 1 of 10 AOZ8001A ultra-low capacitanc e tvs diode array general description the AOZ8001A is a transient voltage suppressor array designed to protect high speed data lines from esd and lightning. this device incorporates four surge rated, low capacitance steering diodes and a tvs in a single package. during transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. they may be used to meet the esd immunity requirements of iec 61000-4-2, level 4. the tvs diodes provide effective suppression of esd voltages up to 30kv (air discharge) and 30kv (contact discharge). the AOZ8001A comes in rohs compliant, sot-143 package and is rated over a -40c to +85c ambient temperature range. it is compatible with both lead free and snpb assembly techniques. the very small sot-143 package is ideal for applications where pcb space is a prem ium. the small size, low capacitance and high esd pr otection makes it ideal for protecting high speed video and data communication interfaces. features esd protection for high-speed data lines: AOZ8001Aji 5v: ? iec 61000-4-2, level 4 (esd) immunity test ? 30kv (air discharge) and 30kv (contact discharge) ? iec 61000-4-5 (lightning) 18a (8/20s) ? human body model (hbm) 30kv AOZ8001Aji 12v: ? iec61000-4-2, level 4 (esd) immunity test ? 30kv (air discharge) and 30kv (contact discharge) ? iec61000-4-5 (lightning) 13a (8/20s) ? human body model (hbm) 30kv small package saves board space low insertion loss protects two i/o lines low capacitance from io to ground: 1.8pf low clamping voltage low operating voltages: 5v, 12v applications usb 2.0 power and data line protection video graphics cards monitors and flat panel displays digital video interface (dvi) 10/100/1000 ethernet notebook computers typical application usb controller +5v d+ d- gnd usb controller +5v d+ d- gnd +12v xdsl AOZ8001Aji-05 1 2 4 3 AOZ8001Aji-12 1 2 +12v +12v tip rj11 ring connector controller figure 1. usb 2.0 high speed port figure 2. xdsl application
rev. 3.0 october 2010 www.aosmd.com page 2 of 10 AOZ8001A ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. pin configuration absolute maximum ratings exceeding the absolute maximum ratings may damage the device. maximum transient rating notes: 1. human body discharge per mil-std-883, method 3015 c discharge = 100pf, r discharge = 1.5k ? . 2. iec 61000-4-2 discharge with c discharge = 150pf, r discharge = 330 ? . maximum operating ratings part number ambient temperature range package environmental AOZ8001Aji-05 -40c to +85c sot-143 rohs compliant green product AOZ8001Aji-12 -40c to +85c sot-143 rohs compliant green product parameter rating storage temperature (t s ) -65c to +150c device hbm (1) esd (contact) (2) esd (air) (2) surge (8/20s) AOZ8001Aji-05 30kv 30kv 30kv 18a AOZ8001Aji-12 30kv 30kv 30kv 13a parameter rating junction temperature (t j ) -40c to +125c sot-143 (top view) 1 2 vn ch1 4 3 vp ch2
rev. 3.0 october 2010 www.aosmd.com page 3 of 10 AOZ8001A electrical characteristics t a = 25c unless otherwise specified. notes: 3. the working peak reverse voltage, v rwm , should be equal to or greater t han the dc or continu ous peak operating voltage level. 4. v br is measured at the pulse test current i t . 5. measurements performed with no external capacitor on v p (pin 4 floating). 6. measurements performed with v p biased to 3.3 volts (pin 4 @ 3.3v). 7. measurements performed using a 100ns tr ansmission line pulse (tlp) system. symbol parameter diagram i pp reverse peak pulse current v cl (5)(7) clamping voltage @ i pp v rwm (3) working peak reverse voltage i r maximum reverse leakage current @ v rwm v br (4) breakdown voltage i f forward current v f forward voltage p pk peak power dissipation c j (6) i/o?gnd capacitance @ v r = 0 and f = 1mhz device device marking v rwm (v) max. v br (v) typ. @ 1ma i r (a) max. v f (v) typ. v cl max. c j (pf) typ. c j (pf) max. i pp = 1a i pp = 5a i pp = 12a AOZ8001Aji-05 ad 5.5 8.5 1.0 0.8 5 12.50 15.00 16.00 1.80 2.50 AOZ8001Aji-12 ad 12.5 15.0 1.0 0 .85 16.00 18.00 19.00 1.80 2.50 i i f i r i t i pp v f v cl v br v rwm v
rev. 3.0 october 2010 www.aosmd.com page 4 of 10 AOZ8001A typical performance characteristics typical variation of c in vs v r (v p = 3.3v, f = 1mhz, t = 25 c) input voltage (v) normalized input capacitance (pf) clamping voltage vs. peak pulse current (t period = 100ns, t r = 1ns) (t period = 100ns, t r = 1ns) peak pulse current, i pp (a) clamping voltage, v cl (v) forward voltage vs. forward current forward current (a) forward voltage (v) i/o ? gnd insertion loss (s21) vs. frequency frequency (mhz) insertion loss (db) i/o ? i/o insertion loss (s21) vs. frequency frequency (mhz) insertion loss (db) crosstalk (i/o?i/o) vs. frequency frequency (mhz) insertion loss (db) -25 -20 -15 -10 -5 0 5 1 10 100 1000 100 0 -25 -20 -15 -10 -5 0 5 1 10 100 1000 100 0 -120 -100 -80 -60 -40 -20 0 110100 1000 10000 o 0 5 10 15 0 2 4 6 0 2 4 6 8 101214 0.0 0.2 0.4 0.6 0.8 1.0 1.2 012345678910 12v 5v 0 2 4 6 8 10 12 14 16 18 20 5v 12v
rev. 3.0 october 2010 www.aosmd.com page 5 of 10 AOZ8001A application information the AOZ8001A tvs is design to protect two data lines from fast damaging transient over-voltage by clamping it to a reference. when the tr ansient on a protected data line exceed the reference voltage the steering diode is forward bias thus, conducting the harmful esd transient away from the sensitive circuitry under protection. pcb layout guidelines printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. the location of the protection devices on the pcb is the simplest and most important design rule to follow. the AOZ8001A devices should be located as close as possi- ble to the noise source. the placement of the AOZ8001A devices should be used on all data and power lines that enter or exit the pcb at th e i/o connector. in most systems, surge pulses occur on data and power lines that enter the pcb through the i/o connector. placing the AOZ8001A devices as close as possible to the noise source ensures that a sur ge voltage will be clamped before the pulse can be coupled into adjacent pcb traces. in addition, the pcb should use the shortest possible traces. a short trace length equates to low impedance, which ensures t hat the surge energy will be dissipated by the AOZ8001A device. long signal traces will act as antennas to receive energy from fields that are produced by the esd pulse. by keeping line lengths as short as possible, the efficien cy of the line to act as an antenna for esd related fields is reduced. minimize inter- connecting line lengths by placing devices with the most interconnect as close together as possible. the protec- tion circuits should shunt t he surge voltage to either the reference or chassis ground. shunting the surge voltage directly to the ic?s signal ground can cause ground bounce. the clamping performance of tvs diodes on a single ground pcb can be improved by minimizing the impedance with relatively short and wide ground traces. the pcb layout and ic pack age parasitic inductances can cause significant overshoot to the tvs?s clamping voltage. the inductance of the pcb can be reduced by using short trace lengths and multiple layers with separate ground and power planes. one effective method to minimize loop problems is to incorporate a ground plane in the pcb design. the AOZ8001A ultra- low capacitance tvs is designed to protect four high speed data transmission lines from transient over-volt- ages by clamping them to a fixed reference. the low inductance and construction minimizes voltage over- shoot during high current surges. when the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. good circuit board layout is critical for the suppression of esd induced transients. the following guidelines are recommended: 1. place the tvs near the io terminals or connectors to restrict transient coupling. 2. fill unused portions of the pcb with ground plane. 3. minimize the path length between the tvs and the protected line. 4. minimize all conductive loops including power and ground loops. 5. the esd transient return path to ground should be kept as short as possible. 6. never run critical signals near board edges. 7. use ground planes whenever possible. 8. avoid running critical si gnal traces (clocks, resets, etc.) near pcb edges. 9. separate chassis ground traces from components and signal traces by at least 4mm. 10. keep the chassis ground trace length-to-width ratio <5:1 to minimize inductance. 11. protect all external connections with tvs diodes.
rev. 3.0 october 2010 www.aosmd.com page 6 of 10 AOZ8001A sim card port connection ieee1394 port connection sim AOZ8001A AOZ8001A AOZ8001A AOZ8001A vcc reset clock i/o gnd ieee 1394 phy ieee 1394 connector tpbiasx tpax+ tpax- tpbx+ tpbx- gnd 1 2 4 3 vcc vcc 1 12 2 3 4 3 4 1 2 3 4
rev. 3.0 october 2010 www.aosmd.com page 7 of 10 AOZ8001A 10/100 ethernet port connection ethernet controller rj45 connector trd0+ trd0- trd1+ trd1- trd2+ trd2- trd3- trd3+ AOZ8001A 12 3 4 AOZ8001A 12 3 4 AOZ8001A 12 3 4 AOZ8001A 12 3 4
rev. 3.0 october 2010 www.aosmd.com page 8 of 10 AOZ8001A package dimensions, sot143-4l notes: 1. all dimensions are in millimeters. 2. tolerances are 0.10mm unless otherwise specified. 3. package body sizes exclude mold flash and gate burrs. 4. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. symbols a a1 b b2 c d e e1 e e1 l1 s dimensions in millimeters min. 0.890 0.013 0.370 0.760 0.085 2.800 2.100 1.200 0.450 0 nom. 1.920 bsc 0.200 bsc 0.550 ref max. 1.120 0.100 0.510 0.940 0.180 3.040 2.640 1.400 0.600 8 dimensions in inches recommended land pattern 1.92 0.70 0.70 0.76 1.05 1.90 0.60 a1 a b2 e1 ee1 s c l1 e d b symbols a a1 b b2 c d e e1 e e1 l1 s min. 0.035 0.001 0.015 0.030 0.003 0.110 0.083 0.047 0.018 0 nom. 0.076 bsc 0.008 bsc 0.022 ref max. 0.044 0.004 0.020 0.037 0.007 0.120 0.104 0.055 0.024 8 unit: mm
rev. 3.0 october 2010 www.aosmd.com page 9 of 10 AOZ8001A tape and reel dimensions, sot143-4l package sot-143 a0 b0 k0 e e1 e2 d0 d1 p0 p1 p2 t 3.10 0.10 0.10 2.69 0.10 1.30 0.10 1.50 1.00 8.00 0.10 1.75 0.05 3.50 0.10 4.00 0.10 4.00 0.05 2.00 0.013 0.254 unit: mm tape reel leader/trailer and orientation +0.30/-0.10 trailer tape 300mm min. components tape orientation in pocket leader tape 500mm min. k0 b0 p0 a0 p1 p2 d0 d1 e1 e2 e t j r feeding direction tape size 8mm reel size ?177.8 m ?177.8 max. n 55.0 min. w1 8.4 +1.50 / -0.0 h 13.0 +0.5 / -0.2 s 1.5 min k 10.1 min. r 12.7 j 4.0 0.1 unit: mm w1 m n s k h +0.25/-0.00
rev. 3.0 october 2010 www.aosmd.com page 10 of 10 AOZ8001A part marking AOZ8001Aji (sot-143) top marking bottom marking adoa assembly location code assembly lot code part number code option code y w lt year & w eek code as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provid ed in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. this datasheet contains preliminary data; supplementary data may be published at a later date. alpha & omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products ar e not authorized for use as critical components in life supp ort devices or systems.
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